Title:
SWITCHING BUS MATRIX
Document Type and Number:
Japanese Patent JPS57141195
Kind Code:
A
Abstract:
A transfer bus matrix provides a single channel of a plurality of conductors to which multiple inputs and multiple outputs are connected by ports or control gates which allow them to be selectively interconnected by control means. Individual matrices or groups of matrices may be involved, including a multistage matrix having individual substage matrices using a transfer bus. Each matrix may be monitored by monitor means having connections to each of the conductors and a multistage matrix may be monitored in each substage and arranged so that each single input may be selectively monitored at various stages throughout the multistage matrix.
Inventors:
RUISU JIEIMUZU SAIDEN
Application Number:
JP21013481A
Publication Date:
September 01, 1982
Filing Date:
December 28, 1981
Export Citation:
Assignee:
T BAR INC
International Classes:
B25B23/14; B25B23/153; G06F13/36; H03K17/00; H04Q3/52; H03K19/177; H04Q3/545; H04Q11/04; (IPC1-7): G06F3/00; H03K17/00; H03K19/00; H04Q3/52