To cope with the reception signal of unknown timing without providing external circuits, and to inhibit increment in circuit scale.
Reference pulse generation circuits 11A and 11B, weighting circuits 12A and 12B, a pulse combining circuit 13, and a PLL oscillator 14 are provided. The reference pulse generation circuits 11A and 11B generate a reference pulse in different timing, based on a reception signal 101 that is subjected to phase modulation. The weighting circuits 12A and 12B assigns weight to reference pulse width, outputted from the reference pulse generation circuits 11A and 11B. The pulse combining circuit 13 combines the output of the weighting circuits 12A and 12B. The PLL oscillator 14 synchronizes with the combined reference pulse for generating a synchronous clock. Weight is assigned to the pulse width, and the combined reference pulse is used, thus eliminating the need for changing the reference pulse and loop characteristics in the PLL oscillator by a selection signal according to the timing of the reception signal, and enabling synchronous and random patterns to be synchronized with a signal having various kinds of timing.
TAKADA MIGAKU
MATSUMOTO ATSUSHI
NARITA TAKANORI
