Title:
SYNCHRONIZATION CIRCUIT
Document Type and Number:
Japanese Patent JP3471275
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a synchronization circuit employing an FIFO that dissolves malfunctions and reduces its circuit scale.
SOLUTION: The synchronization circuit is provided with a Johnson counter 113 that generates a write address to an FIFO 115 synchronously with a CLK 1, a Johnson counter 119, that generates a read address to the FIFO 115 synchronously with a CLK 2, a synchronization flip-flop 116 that synchronizes the addresses, and a decode circuit 118 that generates an FIFO valid means, on the basis of the synchronized addresses.
Inventors:
Someya Masafumi
Application Number:
JP2000032373A
Publication Date:
December 02, 2003
Filing Date:
February 09, 2000
Export Citation:
Assignee:
NEC Electronics Corporation
International Classes:
H04L7/00; H03M7/16; H03M7/22; (IPC1-7): H04L7/00; H03M7/16; H03M7/22
Domestic Patent References:
| JP10242949A | ||||
| JP3203428A | ||||
| JP7202968A |
Attorney, Agent or Firm:
Masahiko Desk (2 outside)
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