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Title:
SYNCHRONIZATION DETECTOR
Document Type and Number:
Japanese Patent JPH0490227
Kind Code:
A
Abstract:

PURPOSE: To surely detect synchronization of a multi-frame signal by detecting respectively a horizontal synchronizing signal and a vertical synchronizing signal of a frame adjustment signal.

CONSTITUTION: One multi-frame MFL consists of 8 sub-multi-frames SMF1-SMF8 and each of the sub-multi-frames SMF1-SMF8 consists of two frames respectively. A frame adjustment signal FAS in 8-bits is arranged to each of frames FLM1-FLM16 and its bit assignment is configurated in the unit of multi-frame MFL. The synchronization of one multi-frame MFL is detected by detecting a horizontal synchronizing signal and a vertical synchronizing signal.


Inventors:
OKOCHI FUSAKICHI
Application Number:
JP20514190A
Publication Date:
March 24, 1992
Filing Date:
August 03, 1990
Export Citation:
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Assignee:
RICOH KK
International Classes:
H04N19/00; H03K23/54; H04J3/00; H04J3/06; H04L7/08; (IPC1-7): H03K23/54; H04J3/00; H04J3/06; H04L7/08; H04N7/13
Attorney, Agent or Firm:
Monda Makoto



 
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