To eliminate the need for an external high speed clock supply source and a clock multiplier circuit by configuring a multiplexer circuit and a demultiplexer circuit with a specific latch circuit and a selector only.
Input data signals D0, D1 at a transmission speed whose phases are not coincident are latched at a trailing of a clock signal by D latches 121-124 of a multiplexer circuit to make the phases are matched with each other. The data signal D1 is latched at a rising of a clock signal by a latch 125 and the phase of the signal D1 is delayed by 1/2-bit. Outputs of the D latches 123, 125 depend on the level of the clock signal by a selector 126. Then one data signal distributed by a demultiplexer circuit is latched by a trailing of a clock signal at D latches 164, 165 and the other data signal is latched at a leading of the clock signal by D latches 161, 162. Furthermore, an output signal of the D latch 162 is latched at a trailing of the clock signal by using the D latch 163 to recover the signals D0, D1 whose phases are arranged.
HANATANI SHOICHI
TAKAI ATSUSHI
