Title:
SYSTEM AND METHOD FOR HANDLING BAD BIT ERRORS
Document Type and Number:
Japanese Patent JP2012221488
Kind Code:
A
Abstract:
To compensate for a bad bit error in a semiconductor nonvolatile memory device.
A device includes a bad bit detection module 116 that receives an old page from a memory device 120 and determines whether the page has a bad bit. The device further includes a bad bit correction module 118 that generates a new page, determines a location of the bad bit. The bad bit correction module 118 determines a preferred value of the bad bit, determines a user value of the bad bit, inserts the preferred value into a string of bits corresponding to substantive data of the old page and record the string of bits with the preferred value inserted therein, and stores the new page at an address of the old page.
Inventors:
BRIAN WILLIAM HUGHES
SHIBATA HIROAKI
YANG WAN-PING
SHIBATA HIROAKI
YANG WAN-PING
Application Number:
JP2012028631A
Publication Date:
November 12, 2012
Filing Date:
February 13, 2012
Export Citation:
Assignee:
DENSO CORP
DENSO INT AMERICA INC
DENSO INT AMERICA INC
International Classes:
G06F12/16; G11C16/02; G11C16/06
Domestic Patent References:
| JP2006048777A | 2006-02-16 | |||
| JP2010140261A | 2010-06-24 |
Attorney, Agent or Firm:
Kazuyuki Yahagi
Taihei Nonobe
Takanori Kubo
Taihei Nonobe
Takanori Kubo
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