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Patent Searching and Data


Title:
SYSTEM AND METHOD FOR PRODUCING SEMICONDUCTOR MEMORY
Document Type and Number:
Japanese Patent JP2001267389
Kind Code:
A
Abstract:

To provide a semiconductor memory production system that can maintain data required for process analysis each lot in time series by a small amount of information, and at the same time can control production based on accumulated data without having to newly carry out measurements.

This semiconductor memory production system tests a semiconductor memory, and is composed of the address of the memory cell of each chip, an LSI tester 1 that outputs the bit map of pass/fail corresponding to the address, and a failure process-estimating device 34 that extracts the bit address of a fail bit from the bit map, determines a redundant word line at a redundant memory part, a word line replacing a redundant bit line, and the substitution address of the bit line, and estimates process failure according to the substituted word line for each chip, the number of substitution of bit lines, and the statistics analysis of the distribution state of each chip for each wafer. According to the estimated result, feedback is to mode manufacturing line/process, thus preventing nonconforming articles from occurring frequently in advance.


Inventors:
OGAWA SUMIO
HARA SHINICHI
Application Number:
JP2000079020A
Publication Date:
September 28, 2001
Filing Date:
March 21, 2000
Export Citation:
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Assignee:
HIROSHIMA NIPPON DENKI KK
International Classes:
H01L21/00; G05B19/418; G06Q50/00; G06Q50/04; G11C29/44; G11C29/56; H01L21/02; H01L21/66; (IPC1-7): H01L21/66; G05B19/418; G06F17/60; G11C29/00; H01L21/02
Attorney, Agent or Firm:
Nobuo Takahashi (3 outside)