Title:
TEMPERATURE COMPENSATING CIRCUIT AND FET AMPLIFIER
Document Type and Number:
Japanese Patent JP3918090
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide an FET amplifier with minimized degradation of distortion property, in response to a change in operating environment temperature.
SOLUTION: An LDMOS (Lateral Diffused MOS) FET1, having a grounded source terminal, operates as a source-grounded amplifier through the application of a gate voltage Vgs from a gate bias terminal 3 via a temperature compensating circuit 2 and a choke coil and through the application of a drain voltage Vds from a drain bias terminal 4 via the choke coil, respectively. The temperature compensating circuit 2 is configured with resistances for parallel-connected fixed resistor elements 21, 22 as the identical values or values in the identical order of magnitudes, and with resistances for thermal elements (thermistors) 23, 24 as a combination of larger values in the order of magnitude and a smaller value in the order of magnitude than the fixed resistor elements 21 or the fixed resistor elements 22, in a standard temperature for the operating environment temperature range (+25°C).
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Inventors:
Amano Shigeru
Application Number:
JP2002020320A
Publication Date:
May 23, 2007
Filing Date:
January 29, 2002
Export Citation:
Assignee:
NEC
International Classes:
H03F1/30; H03F3/193; (IPC1-7): H03F1/30; H03F3/193
Domestic Patent References:
| JP47001035U | ||||
| JP2000275281A | ||||
| JP62091008A | ||||
| JP8307160A |
Foreign References:
| WO2000044089A1 |
Attorney, Agent or Firm:
Masahiko Desk
Naoki Shimosaka
Yasuhisa Tanizawa
Naoki Shimosaka
Yasuhisa Tanizawa