Title:
TEST METHOD FOR LOGICAL UNIT SYSTEM
Document Type and Number:
Japanese Patent JPS5330245
Kind Code:
A
Abstract:
PURPOSE: To realize a test without any collation circuit available by flowing a test data once to each accessory unit and central control unit CC and receiving the data at CC. As a result, the test accuracy can be enhanced for the unit which contains a common circuit.
Inventors:
KISHI SEISHICHI
OONISHI NOBORU
OOTSU YOSHIKATSU
OOMA TOSHIO
KUMAGAI YUKIO
OONISHI NOBORU
OOTSU YOSHIKATSU
OOMA TOSHIO
KUMAGAI YUKIO
Application Number:
JP10523476A
Publication Date:
March 22, 1978
Filing Date:
September 02, 1976
Export Citation:
Assignee:
NIPPON TELEGRAPH & TELEPHONE
FUJITSU LTD
FUJITSU LTD
International Classes:
G06F11/16; G01R31/00; G01R31/28; G06F11/00; G06F15/16; G06F15/177; (IPC1-7): G01R31/00; G01R31/28; G06F11/00; G06F15/16