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Patent Searching and Data


Title:
TEST METHOD OF MEMORY CIRCUIT
Document Type and Number:
Japanese Patent JPS5379329
Kind Code:
A
Abstract:

PURPOSE: To reduce a capacitor of registers at memory circuit test considerably by inibiting comparison between the output of a tested memory circuit and expectation data only when comparison inhibition data exists in both of a column register and a row register.


Inventors:
NARUMI NAOAKI
OOGUCHI OSAMU
ISHIKAWA KOUJI
Application Number:
JP15494876A
Publication Date:
July 13, 1978
Filing Date:
December 24, 1976
Export Citation:
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Assignee:
NIPPON TELEGRAPH & TELEPHONE
International Classes:
G11C29/00; G06F11/22; G11C29/44; (IPC1-7): G11C29/00