PURPOSE: To reduce the number of test data patterns to be prepared beforehand by inputting one test data pattern into a flip flop group of a test circuit being gradually disintegrated once it is set into a shift register.
CONSTITUTION: N pieces of input test data D1, D2... are inputted into the shift register 2 and the data memorized at the top stage are gradually set into respective flip flops selected through a scan-in terminal SI of the test circuit 1. The selection of the respective flip flops is performed with the address counter 3. The results of the computation set into the respective flip flops are gradually transferred to the shift register 2 which transmits the resuts Q1, Q2...Qn at a time. The input test data D1', D2' ...Dn' are applied direct into an input terminal CI of the test circuit 1 and the results of the computation Q1', Q2'...Qn' are outputted from an output terminal CO. Based on these data, the test is executed.
WADA KIYOSHI
MIDORIKAWA ICHIROU
| JPS5455141A | 1979-05-02 |