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Title:
TESTING DEVICE AND METHOD FOR SEMICONDUCTOR INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JP2006162285
Kind Code:
A
Abstract:

To provide a testing device and a method for a semiconductor integrated circuit having high practicality and versatility.

This testing device 2 for the semiconductor integrated circuit has functions described as follows: a test program transmitted from HC 18 is sorted into test condition setting data and test circuit construction data, and stored in DRAM 22 and a flash memory 23 respectively; a desired test circuit 19 is constructed in FPGA 13 based on the test circuit construction data; an inspection waveform signal is generated by an inspection waveform signal generation circuit 30 and outputted to DUT 20 based on the test condition setting data; an output waveform signal outputted from the DUT 20 relative to the inspection waveform signal is compared with a theoretical value by a comparison circuit 31, to thereby determine quality of DUT 20 operation; and a determination result is transmitted to the HC 18.


Inventors:
OTSUKA NOBUYUKI
Application Number:
JP2004350120A
Publication Date:
June 22, 2006
Filing Date:
December 02, 2004
Export Citation:
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Assignee:
INNOTECH CORP
International Classes:
G01R31/28
Domestic Patent References:
JP2003066123A2003-03-05
JP2004037278A2004-02-05
JPH1048296A1998-02-20
JP2004260188A2004-09-16
JP2002311095A2002-10-23
JP2004199537A2004-07-15
JP2005301370A2005-10-27
Attorney, Agent or Firm:
Kazunori Kobayashi