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Patent Searching and Data


Title:
TESTING SYSTEM FOR READING ERROR CORRECTING FUNCTION
Document Type and Number:
Japanese Patent JPS5827220
Kind Code:
A
Abstract:

PURPOSE: To enable correction of reading error by a pseudo input/output device and facilitate testing, by using an IC in place of a reading medium of an input/ output device and performing correction of errors when the frequency of occurrence of errors attains a required frequency.

CONSTITUTION: A pseudo input/output device consisting of an IC memory 2 that is substitutive for the reading medium of an input/output device 1 and a controlling section 3 is connected to a channel device CHC or an input/output controlling device IOC. Error address is written in an error address register 5 from outside. This address and address generated successively from an error address generator 4 are compared and when the two addresses are coincident, an error generation signal is generated from FF11. When the frequency of generation of errors thus detected attains a set value set in a setting circuit 9, a frequency comparator circuit 10 operates to correct the error, and confirms the operation of the channel device CHC or the input/output controlling device IOC.


Inventors:
ADACHI YUUTA
Application Number:
JP12452081A
Publication Date:
February 17, 1983
Filing Date:
August 08, 1981
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
G06F11/08; G06F11/00; G06F13/00; (IPC1-7): G06F3/00; G06F11/22
Attorney, Agent or Firm:
Koshiro Matsuoka