To provide a thin film magnetic storage device that secures a high signal margin during data readout adaptively to variance in manufacture.
A dummy memory cell DCP includes two cell units CU0 and CU1. The cell units CU0, CU1 have configurations similar to that of a memory cell, and each include a tunnel magnetic resistance element and an access transistor ATR coupled in series between a bit line BL and a ground voltage Vss. Different stored data "0" and "1" are written to the cell units CU0, CU1 respectively. In the data readout, the two cell units CU0, CU1 are connected in parallel between the bit line BL and ground voltage Vss for transmitting a readout reference voltage Vref. Further, a constant current which is twice as large as a sense current Is supplied from a current supply circuit 52 to the memory cell, i.e. 2*Is is supplied to the dummy memory cell DCP.
JP2002522864A | 2002-07-23 | |||
JP2002541607A | 2002-12-03 | |||
JP2002541608A | 2002-12-03 | |||
JP2000163950A | 2000-06-16 | |||
JP2002032983A | 2002-01-31 | |||
JP2002522864A | 2002-07-23 | |||
JP2002541608A | 2002-12-03 | |||
JP2002541607A | 2002-12-03 |
WO2000060600A1 | 2000-10-12 | |||
WO2000060601A1 | 2000-10-12 | |||
WO2000008650A1 | 2000-02-17 | |||
WO2000060601A1 | 2000-10-12 | |||
WO2000060600A1 | 2000-10-12 |