Title:
THREE-LEVEL INVERTER DEVICE
Document Type and Number:
Japanese Patent JP3407198
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To suppress the resonance current of the DC bus of a three-level inverter device, and to improve conversion efficiency and operation stability.
SOLUTION: This inverter device is equipped with a converter 1, that converts AC supply power into DC power, an inverter 2 that converts converted DC power into an AC power, and a DC link 3 that connects the converter to the inverter. The DC link 3 has two smoothing capacitors 4a and 4b that are connected between positive-electrode and negative-electrode potential buses P and N in series and store the DC power obtained by the capacitor 1, and two smoothing capacitors 4c and 4d that are connected between the positive- electrode and negative-electrode potential buses P and N in series and store the DC power that is supplied to the inverter 2. In the positive-electrode and negative-electrode potential buses, reactors 7a and 7b for resonance suppression are provided, respectively. In an intermediate potential bus, a resistor 6 for resonance suppression is provided.
Inventors:
Takashi Ikun
Application Number:
JP2000049617A
Publication Date:
May 19, 2003
Filing Date:
February 25, 2000
Export Citation:
Assignee:
株式会社日立製作所
International Classes:
H02M7/12; H02M5/458; H02M7/48; H02M7/483; H02M7/527; H02M7/5387; H02M7/66; H02P27/14; (IPC1-7): H02M7/48; H02M7/12; H02M7/5387
Domestic Patent References:
| JP1118435A | ||||
| JP1146481A | ||||
| JP11355909A |
Attorney, Agent or Firm:
Hiroshi Yoshioka
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