Title:
スルーホールのフィリング方法
Document Type and Number:
Japanese Patent JP6423601
Kind Code:
B2
Abstract:
The methods inhibit or reduce dimpling and voids during copper electroplating of through-holes with flash copper layers in substrates such as printed circuit boards. An acid solution containing disulfide compounds is applied to the through-holes of the substrate followed by filling the through-holes with copper using an acid copper electroplating bath which includes additives such as brighteners and levelers.
Inventors:
Nagarajan Jayaraju
Eli H Nager
Leon Earl Burstad
Eli H Nager
Leon Earl Burstad
Application Number:
JP2014051819A
Publication Date:
November 14, 2018
Filing Date:
March 14, 2014
Export Citation:
Assignee:
Rohm and Haas Electronic Materials LLC
International Classes:
C25D3/38; C25D7/00; C25D5/34
Domestic Patent References:
| JP2009228124A | ||||
| JP2001291954A | ||||
| JP2009041096A | ||||
| JP2010229454A | ||||
| JP2012127003A | ||||
| JP2004250777A |
Attorney, Agent or Firm:
Patent Business Corporation Sender International Patent Office