Title:
TIMING GENERATING DEVICE
Document Type and Number:
Japanese Patent JP3292584
Kind Code:
B2
Abstract:
PURPOSE: To provide a timing generating device which can be transformed into a synchronizing circuit, can be effectively applied to an LSI circuit and also can facilitate its test by generating the timing synchronously with a master clock.
CONSTITUTION: The addresses A (0, m-1) are fetched to a register 1 synchronously with an input pulse CLK, and the data D (0, n-1) are taken out of a storage 3 as the delay data based on the output of the register 1. The delay data are individually stored in the registers 4-1 to 4-k based on the distribution pulses CK1-CKk received from a pulse distribution circuit 2 which successively distributes the pulses CLK to plural paths. Meanwhile the data signals Sli-Ski received fW the registers 4-1 to 4-1 are applied to the delay circuits 6-1 to 6-k through the D/A converters 5-1 to 5-k. Thus the delay times of the delay circuits are controlled, and the pulses CK1-CKk received from the circuit 2 are variably delayed through the circuits 6-1 to 6-k so that the delay pulses CK1X-CKkX are obtained. These delay pulses are taken out through an OR gate 7 in the form of a continuous pulse string.
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Inventors:
Shozo Nitta
Application Number:
JP7053994A
Publication Date:
June 17, 2002
Filing Date:
April 08, 1994
Export Citation:
Assignee:
Toshiba Corporation
International Classes:
H03K5/135; G06F1/06; G11C29/14; (IPC1-7): H03K5/135
Domestic Patent References:
| JP62175012A | ||||
| JP62180607A | ||||
| JP4150515A | ||||
| JP7202656A |
Attorney, Agent or Firm:
Kazuo Sato (3 others)
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