PURPOSE: To make the generation of a timing signal of a cycle different from integer times of a clock cycle possible at a high resolution by comparing a sin wave signal or a cos wave signal obtained from a phase signal generation means with a specified level and generating a delay synchronous pulse.

CONSTITUTION: A sin θ value and a cos θ value are read therefrom on the basis of addition data given from a resistor means 16 in a table memory 21 in connection with a phase signal generation means 20. D/A convertors 22, 23 convert the sing value and the cos θ value read from the table memory 21 into analog signals respectively and these values are output to analog multipliers 24, 25 respectively. An adder 26 adds each multiplication signal from the multipliers 24, 25. A comparator 40 compares the sinθ value and the cos θ value having a phase θ1 output from the phase signal generation means 20 with a specified level. The obtained pulse signal indicates a delay cycle pulse whose phase is successively modified in a cycle of a dividing clock Tc to a clock CLK.