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Title:
【発明の名称】ATM伝送装置
Document Type and Number:
Japanese Patent JP2904698
Kind Code:
B2
Abstract:
PURPOSE:To verify transmission delay quantity control state by FPAC through the use of a measurement P cell by adjusting a transmission delay quantity setting value for the measurement P cell with the FPAC even when the transmission delay is measured by the measurement P cell. CONSTITUTION:A FPAC/TSI extract circuit 7 extracts an FPAC and a TSI from a P cell of a TS addressed to its concerned station. A TSI busy state detection circuit 8 detects a TS busy state display from the extracted TSI. A P cell transmission circuit 15 and a user cell transmission circuit 14 send the burst signal of a measurement P cell (P cell only) as a transmission delay time measurement cell for a TS when the TS is not in use. When the TS is in use, (P cell + user information) is sent in an incoming TS whose number is the same as the TS. An FPAC validity detection circuit 9 detects whether or not an FPAC valid display set by an SLT is valid to control a transmission delay.

Inventors:
ISHII SEISHIRO
MOGI MASAHIDE
AOYANAGI SHINICHI
Application Number:
JP30596993A
Publication Date:
June 14, 1999
Filing Date:
November 11, 1993
Export Citation:
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Assignee:
ANRITSU KK
NIPPON DENSHIN DENWA KK
International Classes:
H04L7/08; H04L12/26; H04L12/28; H04L12/44; H04Q3/00; (IPC1-7): H04L12/28; H04L12/26; H04L12/44
Domestic Patent References:
JP7135507A
JP6326723A
JP5336143A
JP5300166A
JP4241537A
Other References:
1991年信学秋季大会、B−477、p.3−196
1992年信学春季大会、B−725、p.3−292
1993年信学秋季大会、B−668、p.3−307
信学技報、SSE91−121、p.49−54