Title:
【発明の名称】アービタ回路
Document Type and Number:
Japanese Patent JP2900994
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To realize the circuit for avoiding malfunctions caused by a metastable operation of a logic gate resulting from contention of request signals, being input signals with a simple configuration in the arbiter circuit consisting of latch circuits with input/output cross coupling logic gates. SOLUTION: Transistors(TRs) 113, 116 of a conduction type opposite to that of TRs 101, 102, 103, 104 are connected between each gate output point and each series connecting point of the series connection TRs 101, 102 and 103, 104 of each output stage of NOR logic gates 1,2. Then gates and sources of the TRs 113, 116 are in cross-connection, and each drain outputs respectively enable signals AX, AY. Thus, the metastable operation is avoided, having only to add the two TRs.
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Inventors:
OKAMOTO FUYUKI
Application Number:
JP20087696A
Publication Date:
June 02, 1999
Filing Date:
July 31, 1996
Export Citation:
Assignee:
NIPPON DENKI KK
International Classes:
G06F13/18; G06F13/362; H03K3/037; H03K19/0175; (IPC1-7): H03K19/0175
Attorney, Agent or Firm:
Yanagi Kawa Shin