Title:
【発明の名称】2進カウンタ
Document Type and Number:
Japanese Patent JP2563460
Kind Code:
B2
Abstract:
A 1.2 mu m CMOS binary counter having a 200 MHz clock rate comprises a 4-bit counting section that may be concatenated in multiple 4-bit sections. Each bit stage within a 4-bit counter section uses the current state of such stage to determine what happens in the next stage. Each 4-bit section performs the counting function through a successive process of additions of a lowest order carry-bit input. A count enable signal serves to enable the count process as well as serving as a carry-bit input to a first stage. Count enable effects a counter reset when in a logic "zero" state. Once the count enable is raised to the logic "one" state, the process of counting begins with the rising edge of the first clock pulse. As long as the count enable is maintained, counting continues. When the count enable is reduced to a "zero" state, counting is terminated, with a counter reset occurring on the next sequential rising edge of the clock.
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Inventors:
EDOWAADO TEII RUISU
Application Number:
JP8113988A
Publication Date:
December 11, 1996
Filing Date:
April 01, 1988
Export Citation:
Assignee:
RAYTHEON CO
International Classes:
H03K3/356; H03K23/00; H03K21/17; H03K23/40; H03K23/50; H03K23/52; (IPC1-7): H03K23/50
Domestic Patent References:
| JP6010922A | ||||
| JP59221031A | ||||
| JP62151023A | ||||
| JP5227348A | ||||
| JP6084015A | ||||
| JP6124330A |
Other References:
【文献】米国特許3943378(US,A)
【文献】米国特許4037085(US,A)
【文献】米国特許4037085(US,A)
Attorney, Agent or Firm:
Kyozo Yuasa (4 outside)