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Title:
SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF
Document Type and Number:
Japanese Patent JPS6049674
Kind Code:
A
Abstract:

PURPOSE: To estimate the characteristics of FETs with high accuracy in a manufacturing process for a semiconductor by mutually forming channel regions for the FET as a circuit element and the FET as a monitor element equally onto a semiconductor base body.

CONSTITUTION: A resist film is formed onto a semi-insulating GaAs substrate 21, and Si ions are implanted to regions 23a, 23b. A resist film 24 is formed and openings are shaped onto a source region 25 and a drain region 26 for a monitor element, and Se ions are implanted. A Schottky junction is formed between the N type regions 23a and 23b. Gate electrodes 28a and 28b in the same size for a circuit element and the monitor element and a source electrode 29 and a drain electrode 30 for the monitor element are formed. The characteristics of the monitor element can be measured under the state. Si+ ions are implanted into a source region 32 and a drain region 33 for the circuit element and a region 34 and a region 35 for the monitor element to activate them. The characteristics can be measured again at the point of time.


Inventors:
SUZUKI HIDETAKE
Application Number:
JP15736383A
Publication Date:
March 18, 1985
Filing Date:
August 29, 1983
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
H01L29/812; H01L21/265; H01L21/338; H01L21/66; H01L29/80; (IPC1-7): H01L21/265; H01L21/66
Attorney, Agent or Firm:
Sadaichi Igita



 
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