Title:
【発明の名称】カウンタ回路
Document Type and Number:
Japanese Patent JPH07120267
Kind Code:
B2
Abstract:
A counter which is capable of performing a high-speed operation, through utilization of radix-N, for example radix-2, Signed-Digit redundancy representation, with a certain delay time of operation regardless of an increase in the desired count value. The counter comprises an initial value generator (17); a preset circuit (2) for presetting an initial value calculated by the initial value generator; an adder circuit (1) formed by plural digits of radix-N Signed-Digit adders, each including an adder, a transfer digit generator and an interim sum generator; and a circuit for detecting an overflow at a specified digital position.
Inventors:
Tadashi Nakanishi
Hiroki Yamauchi
Hiroki Yamauchi
Application Number:
JP4961687A
Publication Date:
December 20, 1995
Filing Date:
March 04, 1987
Export Citation:
Assignee:
Nippon Telegraph and Telephone Corporation
International Classes:
G06F7/494; G06F7/49; G06F7/508; H03K23/00; H03K23/66; (IPC1-7): G06F7/49; H03K23/66
Domestic Patent References:
| JP6126332U |
Other References:
電子通信学会論文誌Ｊ６７−Ｄ〔４〕（１９８４）Ｐ．４５０−４５７
Attorney, Agent or Firm:
Kugoro Tamamushi (2 outside)