PURPOSE: To detect and correct an error in a smaller number of parity bits by a simple circuit.
CONSTITUTION: Regarding word data which is selected by a row address AR, four parities in the X-axis direction are found by a selector 14x for parity and by a parity generation circuit 15x. Four parities in the Y-axis direction are found by a selector 14y for parity and by a parity generation circuit 15y. Four parities in the Z-axis direction are found by a selector 14z for parity and by a parity generation circuit 15z. When errors are caused in a bit for the word data, the parities in the X-axis, Y-axis and Z-axis directions which contain the errors are combined, bit positions in which the errors have been caused are detected, and the errors are corrected by an error correction part 22b. A total of 4×3=12 are sufficient as the parities which are required.