Title:
REFRESHING SYSTEM OF DYNAMIC MEMORY
Document Type and Number:
Japanese Patent JPS5945690
Kind Code:
A
Abstract:
PURPOSE: To refresh a dynamic RAM easily and securely by utilizing the low- order digit bits of an address.
CONSTITUTION: The low-order digit bits of an address is replaced with a column address while made to correspond to a row address, and refreshing operation is performed. Then the refreshing operation is performed limitedly to once for every row in order to prevent excessive refreshing operation while the same address is repeated by as many times as the number of rasters on every row. Consequently, the need for a switching logic is eliminated because of the common use of a refresh address and no collision of access occurs, thereby refreshing the RAM easily and securely.
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Inventors:
CHIBA KENSHIYOU
Application Number:
JP15567682A
Publication Date:
March 14, 1984
Filing Date:
September 06, 1982
Export Citation:
Assignee:
CHIBA KENSHIYOU
International Classes:
G11C11/406; G11C11/34; (IPC1-7): G11C11/34