PURPOSE: To improve an integrating density and speed by using a new data compressing circuit.
CONSTITUTION: The data compressing circuit 30 is provided with a first, second means 33-A, 33-B executing a logical operation and an OR executing means 34. A first expecting data signal EXDATA1 is compressed together with the odd number of data out signals DOUT 1, 3,..., and the complement/EXDATA1 of the expecting data signal is compressed together with the complement/DOUT 1, 3,... of the odd number of data out signal with the first means 33-A, whereby the first compressed output signal G1 is generated. The second expecting data signal EXDATA0, the even number of data out signals DOUT2, 4,... and these complement/EXDATA0,/DOUT2, 4,... are compressed in the same way with the second means 33-B, whereby the second compressed output signal G2 is generated. The logical sum of the first, second compressed output signals G1, 2 is executed with the OR executing means 34.
| JPH03166822 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE |
| JPH0729398 | SEMICONDUCTOR MEMORY |
| JPH04252491 | SEMICONDUCTOR MEMORY |
FUREDERITSUKU JIYORII
SUCHIYUAATO RAPOPOOTO
| JPH02146199A | 1990-06-05 | |||
| JPH04356799A | 1992-12-10 | |||
| JPH04113580A | 1992-04-15 |