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Title:
MALFUNCTION DETECTING METHOD FOR MPU
Document Type and Number:
Japanese Patent JPH0652007
Kind Code:
A
Abstract:

PURPOSE: To improve the operation efficiency of a microcomputer system by executing a noise as a malfunction, only when an operation failure whose self- recovery is impossible even by an initializing operation is generated, in an MPU of the system.

CONSTITUTION: When an operation failure of a microprocessor MPU 1 is not recovered is spite of a fact that an output Qm-P of a watched timer 2 executes an initializing operation of the MPU 1, and a fact that the number of times of an output of the output Qm-P of the watched timer 2 reaches N is counted by an N-scale number circuit 11, Qn-P of a counting circuit 11 is outputted. This output Qn-l is a malfunction detecting output of the MPU 1, and when the number of times N of counting of the N-scale number counting circuit is selected suitably is advance, it can be decided that an unrecoverable operation failure is generated in the MPU 1. Accordingly, by driving a malfunction display circuit 12 by this Qn-P, a fault of the MPU 1, and also, a microcomputer system is displayed.


Inventors:
SHIOZAWA RYOJI
KUMAZAKI MOTOSUMI
Application Number:
JP20353392A
Publication Date:
February 25, 1994
Filing Date:
July 30, 1992
Export Citation:
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Assignee:
HITACHI DENSHI SERVICE KK
International Classes:
G06F11/22; G06F11/30; (IPC1-7): G06F11/22; G06F11/30
Domestic Patent References:
JPH0218633A1990-01-22
JPS62172441A1987-07-29
Attorney, Agent or Firm:
Takeo Agata



 
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