PURPOSE: To provide an interface device which is small in scale between a single-clock-phase synchronous system and a 4-cycle asynchronous system.
CONSTITUTION: When (reqi) and (acki) are 0, synchronous-side (dataout) is sent to an asynchronous side (datain) and when a clock is 1, the reqi becomes 1 and the datain is latched and inputted to the asynchronous side; when the acki becomes 1, the dataout is sent to the datain and when the clock is 1, the reqi becomes 0 and the datain is latched and inputted to the asynchronous side. When the (acki) becomes 0, a return to an initial state is made and when an (acko) and a (reqo) are 0, the datain is latched and inputted to the synchronous side; when the reqo becomes 1, the asynchronous-side dataout is sent to the datain and when the clock is 1, the acko becomes 1 and the datain is latched and inputted to the synchronous side. When the reqo becomes 0, the dataout is sent to the datain and when the clock is 1, the acko becomes 0.
HANAWA MAKOTO
UCHIYAMA KUNIO
