Title:
【発明の名称】メモリアドレス制御装置
Document Type and Number:
Japanese Patent JP2609628
Kind Code:
B2
Abstract:
PURPOSE: To attain address control for an enlarged/reduced display by hardware and to shorten the time of a CPU occupied by address control by finding out an address by subtraction/addition processing and inclination control processing. CONSTITUTION: In the case of enlarging the display of an area R1 on a display screen E, a fixed value is subtracted from address data outputted from counters 12, 13 for successively generating address data for a picture memory 11 so that address data become '0' on the center position of the area R1, the inclination of the address data is set up to 1/2 and a fixed value is added to the inclination control output to obtain address data for an area R2. In the processing, the device can be almost composed of hardware and a CPU 11 can execute address control only by setting up data in latch circuits 15 to 18 and an area control part 31.
Inventors:
Noriya Sakamoto
Application Number:
JP23676487A
Publication Date:
May 14, 1997
Filing Date:
September 21, 1987
Export Citation:
Assignee:
Toshiba Corporation
International Classes:
G09G5/00; G06F3/153; G06T1/60; G06T3/40; G09G1/00; G09G1/02; G09G5/36; G09G5/39; (IPC1-7): G09G5/36; G06T3/40; G09G5/36
Domestic Patent References:
| JP61290481A | ||||
| JP6226034B2 |
Attorney, Agent or Firm:
Takehiko Suzue (2 outside)