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Title:
MANUFACTURE OF INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JPS587878
Kind Code:
A
Abstract:

PURPOSE: To improve the stability performance by selectively etching only an emitter region forming surface for increasing the leakage current of hFE and then diffusing an impurity for forming the emitter region simultaneously with the other region.

CONSTITUTION: After an emitter region forming surface for increasing relatively a leakage current of hFE is selectively etched, an impurity for forming an emitter region is diffused. For example, a parallel circuit of a transistor 3 operating with the hFE and a transistor 4 operating opposite to hFE is connected between the gate and the source of an impedance converting junction type field effect transistor. After the surface of the emitter region forming part 34 of the transistor 4 operating with opposite hFE of an integrated circuit is selectively etched, and the emitter regions 40, 41 of the respective transistors of the parallel circuit and the gate region 39 of the field effect transistor are simultaneously diffused with impurity.


Inventors:
OKANO JIYUNICHI
MATSUMOTO KIYOTO
Application Number:
JP10532981A
Publication Date:
January 17, 1983
Filing Date:
July 06, 1981
Export Citation:
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Assignee:
TOKYO SHIBAURA ELECTRIC CO
International Classes:
H01L21/331; H01L21/337; H01L29/73; H01L29/80; H01L29/808; (IPC1-7): H01L29/66
Attorney, Agent or Firm:
Takehiko Suzue