PURPOSE: To reduce an interpolation error and the hardware configuration when linear interpolation is applied to a digital signal.

CONSTITUTION: First and second flip-flop circuits 1, 2 are connected in cascade and outputs from them are fed to a next stage subtractor 3, where they are subject to difference operation. The difference is given to an adder 4, the difference whose high-order bits are extended is received by a next stage 3rd flip-flop 5. The high-order bits except the extended bits are obtained as an interpolation output for a small clock period. Simultaneously data whose high-order bits are extended are fed back to the input of the adder 4.