PURPOSE: To obtain the structure of a vertical type J-FET, which can be integrated to a high degree, by burying a gate electrode between a semiconductor layer buried in a first insulating isolation layer and a semiconductor layer buried in a second insulating isolation layer.

CONSTITUTION: Grooves are formed to a semi-insulating high-resistance substrate 1 through etching, and oxide films are attached on the side surfaces of crest sections to shape first insulating isolation layers 2. First semiconductor layers 3, which bury the grooves of the substrate 1 and are grown in an opitaxial manner, are formed by p type semiconductors. n type diffusion layers are formed through selective diffusion and used as gate electrode layers 4. An insulating layer such as an oxide film is grown on the whole surface, and second insulating isolation layers 5 are shaped through selective etching. Second semiconductor layers 6 are grown through second selective epitaxial growth, and conducted with n type diffusion layer nets for gates through diffusion and used as electrodes 7 for leading out gate electrodes, p type high-concentration diffusion is stopped in second selective epitaxial layers, and electrodes 8 for collecting currents are formed.