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Patent Searching and Data


Title:
VIRTUAL STORAGE CONTROLLER
Document Type and Number:
Japanese Patent JPS581873
Kind Code:
A
Abstract:

PURPOSE: To increase the efficiency for an instruction interrupting process in the case of a TLB fault, by adding a bit to a program status word to display the interruption of a conversion exceptional interruption which is caused by a segment fault and shortening the instruction interrupting process in the conversion exceptional mode.

CONSTITUTION: A bit which displays the interruption of a conversion exceptional interruption caused by a segment fault (SF) is applied to a program status words (PSW) 9', 10' and 11' respectively of a CPU1 and a main storage 3 in addition to the instruction interrupting bit iR. When a segment fault occurs with a TLB fault, the bit iR and the SF are turned on to carry out a fault interruption process. Then if a page fault occurs in the page table reference mode, the bit iR is also turned on. Then the information of the storage 3 is sent back to the CPU1 after the PSW is replaced. An instruction given after the interruption is restarted with each process of two types of fault processes by just a send-back of the information without sending the information back to the CPU1. As a result, the instruction interrupting process is shortened to be performed with high efficiency.


Inventors:
SATOU NOBUYOSHI
Application Number:
JP9998481A
Publication Date:
January 07, 1983
Filing Date:
June 27, 1981
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
G06F12/10; (IPC1-7): G06F13/00; G11C9/06
Attorney, Agent or Firm:
Yutaka Morita