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Patent Searching and Data


Title:
LAMINATED TYPE CHIP VARISTOR
Document Type and Number:
Japanese Patent JPH0645109
Kind Code:
A
Abstract:

PURPOSE: To provide a laminated type chip varistor having reduced mounting space, reduced number of components, unnecessary directivity when mounting on a substrate and improved productivity.

CONSTITUTION: The first inner electrodes 15 and 16 and the second inner electrodes 18 and 19 are buried in a ceramic sintered body 11, the first inner electrodes 15 and 16 are led out to one edge face 11a and other edge face 11b of the sintered body 11, and the input and output electrodes 12 and 13, to be connected to the above-mentioned first inner electrodes 15 and 16, are formed on both edge faces 11a and 11b. Also, a resistor 20, to be connected to both input and output electrodes 12 and 13, is provided on the surface of the sintered body 11. The second inner electrodes 18 and 19 are led out to both edge faces of the side faces 11c and lid of the sintered body 11, and the first and the second ground electrodes 14a and 14b, to be connected to the second inner electrodes 18 and 19, are formed on the above-mentioned both edge faces. As a result, a laminated type chip varistor 10 can be constituted.


Inventors:
USHIRO TOMOAKI
NAKAMURA KAZUYOSHI
Application Number:
JP19400692A
Publication Date:
February 18, 1994
Filing Date:
July 21, 1992
Export Citation:
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Assignee:
MURATA MANUFACTURING CO
International Classes:
H01C7/00; H01C7/10; H01C13/02; (IPC1-7): H01C7/10; H01C7/00; H01C13/02
Attorney, Agent or Firm:
Tsutomu Shimoichi