Title:
【発明の名称】半導体記憶素子
Document Type and Number:
Japanese Patent JP2824089
Kind Code:
B2
Abstract:
PURPOSE:To shorten the static characteristic testing time, and simultaneously to attain the guarantee of the static characteristic for a long period by refreshing the content of a main memory element between the main memory element and an auxiliary memory element at the ordinary mode time. CONSTITUTION:By a write signal W three states invertor 12 of a main memory circuit 10 is opened and data are written to a main FF 11. Next, by a refresh read signal RR the three states inverter 23 is opened, the content of the main FF 11 is written to an auxiliary FF 21 of the auxiliary memory circuit 20. And then, by a refresh write signal RW the three states inverter 22 is opened, the content of the auxiliary FF 21 is written to the main FF 11, the refresh of the content of the main FF 11 is repeated. Consequently, if the holding time of the main FF 11 is more than the cycle of a lock phi1 used for the charging of a pre-charge line S its content is held on, so that the static characteristic test, is enough to test the static characteristic in the cycle of the clock phi1, the testing time is drastically shortened.
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Inventors:
Toshiyuki Teramoto
Application Number:
JP24266489A
Publication Date:
November 11, 1998
Filing Date:
September 19, 1989
Export Citation:
Assignee:
富士通株式会社
International Classes:
G01R31/28; G11C11/401; G11C11/413; G11C29/00; G11C29/50; G11C29/56; (IPC1-7): G11C29/00; G01R31/28; G11C11/413
Domestic Patent References:
| JP5746400A |
Attorney, Agent or Firm:
Matsumoto Shinkichi