PURPOSE: To normalize the result of a mantissa adder at a high speed by adding a very small amount of hardware.
CONSTITUTION: A mantissa adding system 2 is provided with a mantissa adder 6 and a flag generator. A first decoder 46 offers a first control signal indicating the highest-rank flag of an inactive state. A first shifter 40 sets the bit of the subgroup corresponding to the highest-rank flag to the highest-rank group by shifting the bit group of added results in accordance with the first control signal. A second detector 48 offers a second control signal indicating the non- zero highest-order bit of the highest-order subgroup of the shifted results. A second shifter 42 sets the non-zero highest-order bit as the highest-order bit by shifting the plurality of bits of shifted results in accordance with the second control signal. The output 8 of the second shifter 48 represents normalized results of addition. Shift information N is generated from the first and second control signals by means of logic means 52 and 54.
IEFUDA BORUPAATO
ARITSUKU EINABU
