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Patent Searching and Data


Title:
ERROR INTERRRUPTING SYSTEM
Document Type and Number:
Japanese Patent JPS581249
Kind Code:
A
Abstract:

PURPOSE: To suitably recover the error of a channel device, by providing an error interruption from the channel device to a CPU with the control of a service processor, in an error interruption system for a computer system.

CONSTITUTION: A data transfer device is respectively provided between channel devices 31, 32,...3n and a service processor 4. The processor 4 sequentially scans the devices 31, 32...3n and a monitors the error of each channel device. If an error takes place in any channel, the processor 4 analyzes the content of the error for required error recovery processing. If the recovery of error is impossible, the forced interruption processing section of the error channel to inform the error and the state of channels of content of error to a CPU1 is started and the error interruption from the error channel to the CPU1 is provided.


Inventors:
HIHARA MASAHITO
OKADA TATSUO
Application Number:
JP9838081A
Publication Date:
January 06, 1983
Filing Date:
June 26, 1981
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
G06F9/48; G06F11/07; G06F13/00; (IPC1-7): G06F3/00; G06F9/46
Attorney, Agent or Firm:
Aoki Akira