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Patent Searching and Data


Title:
TEST OF SEMICONDUCTOR MEMORY
Document Type and Number:
Japanese Patent JPH0823016
Kind Code:
A
Abstract:

PURPOSE: To shorten the testing time by reading out the test result stored in a memory when there is a bad memory in a memory array and then eliminating unnecessary tests.

CONSTITUTION: For good products which are judged no problem or remediable by remedy judgement in a pretest, a flag which shows that they are good products is written. For the good products, a pretest is finished by writing the flag (12, 14). Writing of the flag is selected only at a test mode with a redundant bit which is constituted of a programable and non-volatile semiconductor memory cell. A flag which shows a test result of the pretest is read out from the redundant bit and only the chips which are judged good can proceed to the next step (23, 21, 22A). In a function test (22A), test items which overlap those in the pretest are eliminated. In a wafer test, the result of the pretest can be known instantly and therefore the testing time for bad products can be shortened.


Inventors:
MORI NOBORU
SHIMAZAKI MASAMITSU
OKUGAKI AKIRA
Application Number:
JP15594294A
Publication Date:
January 23, 1996
Filing Date:
July 07, 1994
Export Citation:
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Assignee:
MITSUBISHI ELECTRIC CORP
International Classes:
G01R31/28; G11C29/00; G11C29/44; H01L21/66; G01R31/26; (IPC1-7): H01L21/66; G01R31/26; G01R31/28; G11C29/00
Attorney, Agent or Firm:
Soga Doteru (6 people outside)