METHOD OF FORMING NO DEFECT SURFACE LAYER OF SILICON WAFER

Title:

METHOD OF FORMING NO DEFECT SURFACE LAYER OF SILICON WAFER

Document Type and Number:

Japanese Patent JPS603130

Kind Code:

A

Abstract:

A process is disclosed for preparing silicon wafers (10) having a high quality, high lifetime surface layer (21) and a bulk region (23) characterized by a low lifetime and by a high density of precipitated oxygen gettering sites. A wafer having a relatively high concentration of interstitial oxygen is heated in a reducing ambient at a sufficiently high temperature and a sufficiently long time to cause a surface layerto be denuded of oxygen related defects and disclocations. The temperature is then ramped down to a lower temperature and the wafer is maintained at this lower temperature for a sufficient time to allow precipitation of oxygen within the bulk of the wafer.

More Like This:

JP2002050553	SHAPE SIMULATION METHOD AND COMPUTER-READABLE RECORDING MEDIUM WITH PROGRAM FOR SHAPE SIMULATION STORED THEREON
WO/2001/048801	METHOD AND APPARATUS FOR MONITORING POLISHING STATE, POLISHING DEVICE, PROCESS WAFER, SEMICONDUCTOR DEVICE, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
JP4588539	Driver circuit

Inventors:

FUIRITSUPU JIEI TOBIN

Application Number:

JP10353984A

Publication Date:

January 09, 1985

Filing Date:

May 22, 1984

Export Citation:

Click for automatic bibliography generation Help

Assignee:

MOTOROLA INC

International Classes:

H01L21/00; H01L21/316; H01L21/322; (IPC1-7): H01L21/322

Domestic Patent References:

JPS59202640A

1984-11-16

Attorney, Agent or Firm:

Shinsuke Onuki (1 person outside)

Next Patent: JPS603131