PURPOSE: To minimize the occurrence of distortion and, at the same time, to make setting time shorter by installing an emitter follower circuit containing an npn transistor and pnp transistor to a bias voltage generating circuit.

CONSTITUTION: Since transistors (TR) 12 and 13 act as emitter followers and give forward biases of TRs 5 and 6, the TRs 5 and 6 also act as emitter followers, and thus, a two-stage emitter follower constitution is realized. Since a load capacity is driven with the two-stage emitter followers under this condition, the TRs 12 and 13 supply a large capacitive current even when the capacitive current flows to the bases of the TRs 5 and 6. Therefore, the occurrence of distortion is minimized even when the input impedance is somewhat high. Moreover, by improving the driving capacity, the settling time can be made shorter.