Title:
MASTER SLICE INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JPS6074455
Kind Code:
A
Abstract:
PURPOSE:To improve the degree of freedom of the design by a method wherein the fundamental cells, consisting of a power source cell and a switching part, are provided separately and adjoiningly with each other. CONSTITUTION:A pad 10 is provided on the circumference of a semiconductor chip 1, a fundamental cell array 20 whereon a fundamental cell 22 is arranged in matrix form is formed on the inside of said pad 10, and a current source cell 24 which constitutes the current souce is arranged on both sides of the column of the fundamental cell 22. Also, a power source VEE line 50 is wired on the upper and the lower isdes of the array 20 and a power source VCC line 40 is wired on the left and the right sides of the array 20 crossing with each other. A high power consuming gate having a high driving capability even in the fundamental cell array can be constituted by separately and adjoiningly providing the current source cell 24 and the fundamental cell 22.
Inventors:
SUZUKI YUUICHI
AKIYAMA TAKEHIRO
MORITA AKIO
AKIYAMA TAKEHIRO
MORITA AKIO
Application Number:
JP17926583A
Publication Date:
April 26, 1985
Filing Date:
September 29, 1983
Export Citation:
Assignee:
FUJITSU LTD
International Classes:
H01L21/822; G11C11/401; H01L21/82; H01L23/528; H01L27/04; H01L27/118; (IPC1-7): H01L27/04
Domestic Patent References:
| JPS5850768A | 1983-03-25 |
Attorney, Agent or Firm:
Aoki Akira
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