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Patent Searching and Data


Title:
CMOS INTEGRATED CIRCUIT DEVICE
Document Type and Number:
Japanese Patent JPS5925419
Kind Code:
A
Abstract:

PURPOSE: To prevent a through current flowing to a CMOS inverter and to simplify the constitution of a CMOS IC device, by setting the output impedance of an IC device larger than that of plural tristate output circuits.

CONSTITUTION: The input terminal of a CMOS inverter INV as well as output terminals of tristate output circuits TB1∼TB5 of a CMOS IC device are connected in common to a signal bus BUS. The selection signal of a decoder DCR as well as data D1∼D5 are supplied to the circuits TB1∼TB5 respectively. Furthermore the input/output terminal of an FF circuit FF is also connected to the BUS. Then the output impedance of an IC device is set larger than those of the circuits TB1∼TB5. When either one of the circuits TB1∼TB5 is not conductive, the through current flowing to the inverter INV is prevented. Thus the constitution is simplified for the IC device.


Inventors:
UCHIDA MAKIO
Application Number:
JP13372182A
Publication Date:
February 09, 1984
Filing Date:
August 02, 1982
Export Citation:
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Assignee:
HITACHI LTD
International Classes:
H03K19/0175; H03K19/00; (IPC1-7): H03K19/00
Attorney, Agent or Firm:
Toshiyuki Usuda