PURPOSE: To obtain a reproduced signal having reduced timing jitters, by extracting a clock signal after resetting only the recorded and reproduced clock signal that has the reset timing interval longer than the 1st period and shorter than the 2nd period.
CONSTITUTION: Gating is performed with the output of a monostable multioibrator 3 to prevent that a reset pulse is supplied to a counter circuit 5 with ≤4T time interval, where T means the unit bit interval. Thus it is possible to eliminate the effect of variations of a sudden reset timing. The circuit 5 is reset with the above-mentioned reset pulse. The clock information of the output of the circuit 5 has no sudden change and is equal to the information less in varying frequency component due to the traveling of a tape, etc. Such information is fed to a PLL circuit to obtain a reproduced signal having reduced timing jitters.
KIHARA NOBUYOSHI
KATOU MISAO
MATSUSHIMA KOUJI
