PURPOSE: To equalize a read speed regardless of a reduction rate by dividing data into blocks and sampling data in each block according to a reduction rate, and grouping them and storing in plural memories capable of operating in parallel.

CONSTITUTION: Input data is inputted to an S/P shift register 1 and converted into a 4-bit parallel signal, which is shifted cyclically by a shift register 2 and then stored in a memory circuit 4 through a latch 3. The memory circuit 4 consists of four memories M1WM4 capable of operating independently of one another. Data which are divided into blocks and sampled according to the reduction rate are stored in the memories M1WM4 while grouped. Data from the circuit 4 is outputted through a shift register 5, data converting circuit 6, and P/S shift register 7.