PURPOSE: To attain the time division multiplexing of two signals, by delaying one of the inputted two signals, and switching this delayed signal and the non- delay signal with a timing pulse.

CONSTITUTION: A clock input signal C is frequency-divided into 1/2 at a timing pulse generating circuit 9 to obtain a timing pulse 1 and its inverting signal 2 being a low level when a reset pulse PR is a low level. When this timing pulse and a data A1 are applied to a gate 2, the data A1 is obtained at the output. Further, a data B1 of the same timing as the data A1 is latched 4 at the leading edge of the pulse 2, inputted to a gate 5 and the data B1 is outputted in the high level of the timing next to the pulse 2. Thus, the data signals A, B are obtained alternately at the output for time division multiplexing.