PURPOSE: To obtain highly reliable data by setting a more strict tolerance to a deviation in timing during data writing.

CONSTITUTION: When a basic clock is supplied from a phase-locked oscillator 1, a counter 2 outputs signals Q2, Q3 and Q4. The signal Q3 is supplied to the data input terminal D of a D-F/F11, and the signal Q2 is supplied to the clock input terminal CK. The period when a signal I supplied from the D-F/F11 to a D-F/ F12 has a level High is regarded as an error window, and consequently error windows are generated as both ends of a data window. An error detection signal J outputted from the D-F/F12 has the same level with the signal I when a data pulse E is applied to a clock input terminal CK, so the pulse E is entered at such timing that it is in the data window and also in the error window at the same time, the signal J has the level High, which is judged as an error.