Title:
SUBSTRATE VOLTAGE GENERATOR
Document Type and Number:
Japanese Patent JPS59125419
Kind Code:
A
Abstract:
A regulated on-chip substrate-voltage generator circuit converts a single power supply input and ground potential into a negative potential. The negative potential is applied to the substrate of an integrated circuit upon which the substrate-voltage generator is formed. The substrate voltage generator includes a voltage oscillator connected to a charge pump device. A pair of depletion FETs forms a voltage divider circuit between the ground potential and the substrate potential. An amplifier, formed from depletion FETs, couples the voltage divider into the charge pump. The voltage divider and amplifier regulate the charge pump thereby maintaining tight control over the substrate voltage.
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Inventors:
TOOMASU EDOUIN DEIRINJIYAA
TERANSU UEIN KUUPAA
TERANSU UEIN KUUPAA
Application Number:
JP17234983A
Publication Date:
July 19, 1984
Filing Date:
September 20, 1983
Export Citation:
Assignee:
IBM
International Classes:
G05F3/20; G05F3/24; G11C5/14; G11C11/407; H02M3/07; H03K19/094; (IPC1-7): G05F1/56
Attorney, Agent or Firm:
Next student Okada