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Title:
LOGICAL SYSTEM
Document Type and Number:
Japanese Patent JPS5928725
Kind Code:
A
Abstract:

PURPOSE: To realize a fail safe property, by inputting alternating signals having different frequencies depending on respective input truth values and discriminating the outputted truth value depending on whether the input frequency is within a prescribed reference frequency band or not so as to output the alternating signal having the frequency corresponding to the truth value.

CONSTITUTION: A logical element 13 is constituted with an operating section 7, a band discriminating section 8 and an alternating signal generating section 10, and the operating section 7 sums the frequency of the alternating signal and outputs an alternating signal 14. The added alternating signal 14 is added 1 to a frequency comparison circuit 34 and compared with an alternating signal 32 having a reference frequency from an alternating signal generating circuit 30. The circuit 30 generates plural different alternating signals 32 by means of time division and the band discrimination at the circuit 34 is attained. Further, an amplitude comparing and discriminating signal 36 is outputted from the comparison circuit 34, and the alternating signal having a frequency corresponding to the outputted truth value in response to the result of band discrimination is outputted by using the circuit 30 in common and the fail safe property is realized by using a fail-out semiconductor element or the like.


Inventors:
TASHIRO FUSASHI
AKIYAMA HIROYUKI
Application Number:
JP13731282A
Publication Date:
February 15, 1984
Filing Date:
August 09, 1982
Export Citation:
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Assignee:
HITACHI LTD
International Classes:
H03K19/00; H03K19/007; H03K19/20; H03K19/23; (IPC1-7): H03K19/007
Domestic Patent References:
JPS4843468A1973-06-23
JPS55134540A1980-10-20
Attorney, Agent or Firm:
Katsuo Ogawa