Title:
MICROWORD CONTROL SYSTEM
Document Type and Number:
Japanese Patent JPS59121546
Kind Code:
A
Abstract:
Microword control system for use in a microprogrammad data processor (10) in which an encode programmable logic array (270) responds to input signals which instruct system-initiated control operations, such as interrupts, power failure shut-down operations, system reset operations, etc., to produce internal exception condition opcodes applied to inputs of a plurality of system decode programmable logic arrays (251-254) which, in response to the opcodes, generate sequences of microwords for executing the system-initiated control operations. The programmable logic arrays (251-254) are activated sequentially and cyclically to generate the sequences of microwords used to carry out each of the control operations. The outputs of the programmable logic arrays (251-254) are multiplexed onto two data buses (214-218), and the microwords on the two data buses (214-218) are alternately decoded to produce control point signals used to directly control the operations of the processor (10).
Inventors:
JIERAADO EI BUENESUKII
Application Number:
JP19536483A
Publication Date:
July 13, 1984
Filing Date:
October 20, 1983
Export Citation:
Assignee:
IBM
International Classes:
G06F9/22; G06F9/26; (IPC1-7): G06F9/22
Domestic Patent References:
| JPS4951839A | 1974-05-20 | |||
| JPS50105345A | 1975-08-20 | |||
| JPS51852A | 1976-01-07 | |||
| JPS4991737A | 1974-09-02 | |||
| JPS55116147A | 1980-09-06 |
Attorney, Agent or Firm:
Koichi Tonmiya