Title:
INTERFACE INSPECTOR
Document Type and Number:
Japanese Patent JPS608964
Kind Code:
A
Abstract:
Testing of interface lines (14) interconnecting a first circuit (10) to a second circuit. When an abnormal circuit condition affects the interface lines, such as an open circuit or a short circuit condition, the operation of the first and second circuit is detrimentally affected. The present invention determines the existence of abnormal circuit conditions in one or more lines of a group of interface lines without the utilization of redundant duplex lines to perform the determination. The interface lines are subdivided into a first group (14a), which are used when the apparatus of the present invention is being used to locate abnormal circuit conditions, and a second group (14b), which is not used when the apparatus of the present invention is being used to locate abnormal circuit conditions. Each line of the first group is connected to a corresponding input terminal of a first exclusive OR gate (16) and a second exclusive OR gate (18) at an input side and an output side, respectively. The first and second OR gates are input to a matching circuit (20), an output signal therefrom indicating the existence of an abnormal circuit condition in the first group of lines. As a result, since the lines of the first group are used when the apparatus of the present invention is being used to locate abnormal circuit conditions, each line of the first group is tested individually for the presence of an abnormal circuit condition. However, since the lines of the second group are not used when the apparatus of the present invention is locating abnormal circuit conditions, the lines of the second group are tested, collectively, as a group, for the presence of an abnormal circuit condition. One line (11) of the first group is connected to an input side of the second group. The output side of the second group is connected to an additional input terminal of the second exclusive OR gate. An output signal from the matching circuit indicates the existence of an abnormal circuit condition in at least one line of either one or both of the first and second group of lines.
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Inventors:
SUTEFUAN PIITAA JIYAKOUSUKII
JIEEMUZU SEODOA MOIAA
JIEEMUZU SEODOA MOIAA
Application Number:
JP5130184A
Publication Date:
January 17, 1985
Filing Date:
March 19, 1984
Export Citation:
Assignee:
IBM
International Classes:
G01R31/28; G06F11/00; G06F13/00; G06F11/16; G06F13/36; (IPC1-7): G06F13/00; G06F13/36
Domestic Patent References:
| JPS5336436A | 1978-04-04 |
Attorney, Agent or Firm:
Fumio Shinoda
Next Patent: INPUT/OUTPUT BUFFER MEMORY SYSTEM